The present invention relates to a direct memory access (DMA) controlling device, and more particularly, to a DMA controlling device for temporarily granting a priority of memory use to a microprocessor or another master intending to use a source or destination memory during DMA transmission.
The purpose of DMA transmission is to rapidly transmit data from a specific memory to another memory such that a microprocessor can carry out a different task during the DMA transmission, and thus offers more efficient and excellent system performance.
In order to perform the DMA transmission, a DMA controlling device receives a series of instructions from the microprocessor for transmitting data from a specific memory, i.e., a source memory, to another memory, i.e., a destination memory, and then executes the instructions. A conventional DMA controlling device is comprised of a control register for storing an instruction issued from the microprocessor, a source address generator for generating the address of a source memory which stores data to be transmitted, a destination address generator for generating the address of a destination memory in which the data transmitted from the source memory is to be stored, a count register for storing the number of DMA transmissions which should be carried out, a state register for storing a state occurring during DMA transmission, and a DMA controller for controlling the DMA transmission.
When as many DMA transmissions as the number stored in the count register is performed, the DMA controlling device notifies the microprocessor which issued the instruction of the DMA transmissions, and is set to an initial state to wait for the next instruction. If an error takes place during the DMA transmissions, the error is recorded in the state register and an error interrupt is sent to the microprocessor so that the microprocessor can read the state register and take an appropriate action.
As described above, the conventional DMA controlling device supports only the DMA transmission. When a DMA transmission begins, other masters, for example, a microprocessor or other controllers, cannot access to the memories, i.e., source and destination memories which a DMA controller is using, until an assigned number of DMA transmissions have been completed.
To overcome this drawback, a method of making the amount of DMA transmission data smaller is used so that the time required to perform the DMA transmission is reduced.
However, no great progress is made in such a method because a long standby time is still required for a microprocessor to access to a memory. In a system requiring high-speed performance, delay of a response during CPU processing degrades the system performance. Furthermore, in case of a multiprocessor system having a shared memory structure, many masters frequently compete for access to a shared memory.
As a result, the memory processor should wait for an access to a memory until a DMA transmission is completed. To be worse, a timeout which damages the system may be generated, which counteracts the advantages of using the DMA transmission.
The following patents each disclose DMA controllers having features in common with the present invention. However, none of these patents teach or suggest the specific combination of recited features of the present invention:
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